#布线布局脚本
set design riscv_npu_soc
read_verilog ${design}_syn.v
read_sdc ${design}_syn.sdc
read_lib your_lib.lib
floorplan -r 1.0 0.7 20 20 20 20
place_design
route_design
write_gds ${design}.gds
write_def ${design}.def